The P32W Bus¶

Status: IN USE: every card's netlist and the backplane are generated from this definition and checked against it (D50, D52, D57, D59, D64, D68, D74, D76; last change 2026-11-11, D102: -CPUIN and -MMUIN on two of J3's spare pins).

Generated by generators/p32bus.py — edit the generator, not this file.

Three 96-pin DIN 41612 connectors per card (D49), down the 366.7 mm edge of a 9U × 340 mm card: J1 the bus cycle (data, physical address, byte enables, strobes, -ACK, -WAIT), J2 system control (clock, reset, interrupts, arbitration), J3 the CPU ↔ MMU/data local link in slots 1 and 2 and the debug slot 0 (power only in the others). Pins 1–2 of every row are VCC, 31–32 GND; row B odd pins 3–29 are GND (a guard between rows A and C); J2's row B even pins 4–30 are VCC as well (D57), so J2 carries alternate supply pins down its middle. Active-low signals have a leading dash; -ACK, -WAIT, -LOCK and -IRQn are open-drain with backplane pull-ups. Spare pins on J1 and J2 are bused to every slot (D68); J3's eight (B28, B30, C25–C30) join slots 0, 1 and 2, as the local link does (D99): spare private lines. The backplane itself: backplane.md.

The backplane does not carry the CPU's microcode fields: only physical memory cycles, so any card can be a bus master (DMA), any number of memory cards can answer, and a slow card can stretch a cycle.

Pins (per card): 171 signal, 32 VCC, 60 GND, 25 spare (of 288).

The bus cycle¶

The bus is synchronous: one clock (CLK, the CPU's microcycle: 3 MHz, or 4 MHz with the CPU card's clock jumper, D72, D74) for every card. A cycle is one clock, stretched by -WAIT:

          ┌─────┐     ┌─────┐     ┌─────┐
CLK  ─────┘     └─────┘     └─────┘     └────
     │ clock 1   │ wait (opt) │ next cycle
A, BE,    <══ driven by the master, held through the waits ══>
-MRD/-MWR
-ACK      ‾‾‾‾\____________________/‾‾   the addressed card, within clock 1
-WAIT     ‾‾‾‾‾\_______/‾‾‾‾‾‾‾‾‾‾‾‾‾   a slow card: low before clock 1 ends
D (read)  ───────────────<═ valid ═>──   taken at the edge that ends the cycle

The master drives A2–A31, BE0–BE3 and -MRD or -MWR from the start of the clock (on a write, D too).
The addressed card pulls -ACK low within the first clock: address decoding is fast and always fits. No -ACK by the end of the first clock is a BUSERROR, so a missing card can never hang the bus.
A slow card also pulls -WAIT low before the clock ends. The master holds everything for another clock, and checks -WAIT again; when it is high at the end of a clock, that edge ends the cycle (a read's data is taken then; a write is complete).
The CPU sees a waiting cycle as STALL on the local link: its clock CCLK has no edge until the cycle ends, so nothing on the CPU side changes. The microcode does not change for slower cards.

Bus mastership (DMA)¶

The arbiter is on the MMU / data card (slot 2), which is the CPU's own master interface. Any card in slots 3–10 may become master:

It pulls its radial -BREQ low. The arbiter grants at a cycle boundary, when the CPU's next microcycle does not use the bus (most do not: about two in six are memory cycles), and holds the CPU (STALL) only when the CPU wants the bus while a device has it.
-BGNT low means the card is master from the next clock. It runs as many cycles as it likes and gives the bus back by releasing -BREQ; the arbiter then drops -BGNT.
Priority: fixed, among the requests present at the boundary: slot 0 (the debug card, D64) first, then the higher slot first.
-LOCK: a master that holds -LOCK low keeps the bus for the next cycle too; the CPU uses it for an atomic read-modify-write (LOCKREQ on the local link), and the arbiter grants nothing while it is low.
A DMA master addresses physical memory; it has no MMU. The kernel gives it physical buffers (and pins their pages while the transfer runs).

Interrupts¶

-IRQ0–-IRQ7, open-drain levels into the CPU's IMASK / IPEND logic; the lowest-numbered pending, enabled level is taken first (IRQ0, the timer, has the highest priority).
Each card's jumpers choose the level each of its devices drives (D52). Nothing about an interrupt depends on the slot a card is in.
Vectored (D57). When the CPU takes level n, the MMU / data card runs an interrupt acknowledge cycle: a bus cycle like a read, with -IACK low instead of -MRD and A4:A2 = n (the other address bits and BE0–BE3 don't matter). The card driving level n pulls -ACK and puts its vector on D7:D0: its window number (D52) × 16 + the number of its device that is asking (its interrupt status register's bit; the lowest pending one on that level). A level is driven by one card — the jumpers of two cards must not share one — though one card may drive several. No -ACK (no card, or one without vectors) is not a bus error: the vector is 0xFF, and the kernel reads the cards' interrupt status registers instead. The CPU puts the vector into CAUSE bits 15:8.

Slots¶

Slot	Card	J3
0	the debug card (D64): every signal, to listen or drive	the local link, a third drop
1	CPU	the local link
2	MMU / data (and the arbiter)	the local link
3–10	any: memory, disk, I/O, video	power only

The backplane has ten positions, slots 0–9, 1.5 inches apart (D99, docs/backplane.md): the bus's slot 10 has no socket there, and its request pair is unused. Cards go in with their components facing slot 0's end, the front.

Slot 0 carries everything: J1 and J2 as every slot, the radial -BREQ3–10 / -BGNT3–10 as slot 2 sees them (to watch or play every requester), its own pair -BREQ0 / -BGNT0 (the arbiter's highest priority), and J3. The debug card there can watch a running CPU's local link, or, with the CPU card pulled, play the CPU's side of it.

Every card is placed by its jumpers, not its slot (D50, D52): memory cards choose a 16 MiB window, device cards a 4 KiB window among the device registers, and their interrupt levels. Apart from slots 1 and 2 (the local link), any card works in any slot; the slot only sets its bus-request priority.

J1¶

Pin	Row A	Row B	Row C
1	VCC	VCC	VCC
2	VCC	VCC	VCC
3	D0	GND	D28
4	D1	A26	D29
5	D2	GND	D30
6	D3	A27	D31
7	D4	GND	A2
8	D5	A28	A3
9	D6	GND	A4
10	D7	A29	A5
11	D8	GND	A6
12	D9	A30	A7
13	D10	GND	A8
14	D11	A31	A9
15	D12	GND	A10
16	D13	BE0	A11
17	D14	GND	A12
18	D15	BE1	A13
19	D16	GND	A14
20	D17	BE2	A15
21	D18	GND	A16
22	D19	BE3	A17
23	D20	GND	A18
24	D21	-MRD	A19
25	D22	GND	A20
26	D23	-MWR	A21
27	D24	GND	A22
28	D25	-ACK	A23
29	D26	GND	A24
30	D27	-WAIT	A25
31	GND	GND	GND
32	GND	GND	GND

J2¶

Pin	Row A	Row B	Row C
1	VCC	VCC	VCC
2	VCC	VCC	VCC
3	CLK	GND	-BREQ3
4	-CLK	VCC	-BREQ4
5	-RES	GND	-BREQ5
6	PWROK	VCC	-BREQ6
7	-LOCK	GND	-BREQ7
8	-IRQ0	VCC	-BREQ8
9	-IRQ1	GND	-BREQ9
10	-IRQ2	VCC	-BREQ10
11	-IRQ3	GND	-BGNT3
12	-IRQ4	VCC	-BGNT4
13	-IRQ5	GND	-BGNT5
14	-IRQ6	VCC	-BGNT6
15	-IRQ7	GND	-BGNT7
16	-BREQ	VCC	-BGNT8
17	-BGNT	GND	-BGNT9
18	-IACK	VCC	-BGNT10
19	-FAST	GND	-BREQ0
20	XCLK	VCC	-BGNT0
21	-XCLKEN	GND	SPARE_J2C21
22	SPARE_J2A22	VCC	SPARE_J2C22
23	SPARE_J2A23	GND	SPARE_J2C23
24	SPARE_J2A24	VCC	SPARE_J2C24
25	SPARE_J2A25	GND	SPARE_J2C25
26	SPARE_J2A26	VCC	SPARE_J2C26
27	SPARE_J2A27	GND	SPARE_J2C27
28	SPARE_J2A28	VCC	SPARE_J2C28
29	SPARE_J2A29	GND	SPARE_J2C29
30	SPARE_J2A30	VCC	SPARE_J2C30
31	GND	GND	GND
32	GND	GND	GND

J3¶

Pin	Row A	Row B	Row C
1	VCC	VCC	VCC
2	VCC	VCC	VCC
3	LR0	GND	LR28
4	LR1	FAULT	LR29
5	LR2	GND	LR30
6	LR3	FC0	LR31
7	LR4	GND	RSRC0
8	LR5	FC1	RSRC1
9	LR6	GND	RSRC2
10	LR7	FC2	RSRC3
11	LR8	GND	RDST0
12	LR9	FC3	RDST1
13	LR10	GND	RDST2
14	LR11	-WSTB	MEM0
15	LR12	GND	MEM1
16	LR13	STALL	MEM2
17	LR14	GND	SIZE0
18	LR15	LOCKREQ	SIZE1
19	LR16	GND	SIGNED
20	LR17	CCLK	CRSEL0
21	LR18	GND	CRSEL1
22	LR19	PCINC	CRSEL2
23	LR20	GND	SUPER
24	LR21	MARPC	TLBW
25	LR22	GND	SPARE_J3C25
26	LR23	MARINC	SPARE_J3C26
27	LR24	GND	SPARE_J3C27
28	LR25	-CPUIN	SPARE_J3C28
29	LR26	GND	SPARE_J3C29
30	LR27	-MMUIN	SPARE_J3C30
31	GND	GND	GND
32	GND	GND	GND

Signals¶

Signal	Pin	Wired to	Driven by	Read by	Meaning
`D0`	J1 A3	every slot	the master (write) or the addressed card (read)	all	data bus
`D1`	J1 A4	every slot	the master (write) or the addressed card (read)	all	data bus
`D2`	J1 A5	every slot	the master (write) or the addressed card (read)	all	data bus
`D3`	J1 A6	every slot	the master (write) or the addressed card (read)	all	data bus
`D4`	J1 A7	every slot	the master (write) or the addressed card (read)	all	data bus
`D5`	J1 A8	every slot	the master (write) or the addressed card (read)	all	data bus
`D6`	J1 A9	every slot	the master (write) or the addressed card (read)	all	data bus
`D7`	J1 A10	every slot	the master (write) or the addressed card (read)	all	data bus
`D8`	J1 A11	every slot	the master (write) or the addressed card (read)	all	data bus
`D9`	J1 A12	every slot	the master (write) or the addressed card (read)	all	data bus
`D10`	J1 A13	every slot	the master (write) or the addressed card (read)	all	data bus
`D11`	J1 A14	every slot	the master (write) or the addressed card (read)	all	data bus
`D12`	J1 A15	every slot	the master (write) or the addressed card (read)	all	data bus
`D13`	J1 A16	every slot	the master (write) or the addressed card (read)	all	data bus
`D14`	J1 A17	every slot	the master (write) or the addressed card (read)	all	data bus
`D15`	J1 A18	every slot	the master (write) or the addressed card (read)	all	data bus
`D16`	J1 A19	every slot	the master (write) or the addressed card (read)	all	data bus
`D17`	J1 A20	every slot	the master (write) or the addressed card (read)	all	data bus
`D18`	J1 A21	every slot	the master (write) or the addressed card (read)	all	data bus
`D19`	J1 A22	every slot	the master (write) or the addressed card (read)	all	data bus
`D20`	J1 A23	every slot	the master (write) or the addressed card (read)	all	data bus
`D21`	J1 A24	every slot	the master (write) or the addressed card (read)	all	data bus
`D22`	J1 A25	every slot	the master (write) or the addressed card (read)	all	data bus
`D23`	J1 A26	every slot	the master (write) or the addressed card (read)	all	data bus
`D24`	J1 A27	every slot	the master (write) or the addressed card (read)	all	data bus
`D25`	J1 A28	every slot	the master (write) or the addressed card (read)	all	data bus
`D26`	J1 A29	every slot	the master (write) or the addressed card (read)	all	data bus
`D27`	J1 A30	every slot	the master (write) or the addressed card (read)	all	data bus
`D28`	J1 C3	every slot	the master (write) or the addressed card (read)	all	data bus
`D29`	J1 C4	every slot	the master (write) or the addressed card (read)	all	data bus
`D30`	J1 C5	every slot	the master (write) or the addressed card (read)	all	data bus
`D31`	J1 C6	every slot	the master (write) or the addressed card (read)	all	data bus
`A2`	J1 C7	every slot	the master	all	physical address bits 31:2
`A3`	J1 C8	every slot	the master	all	physical address bits 31:2
`A4`	J1 C9	every slot	the master	all	physical address bits 31:2
`A5`	J1 C10	every slot	the master	all	physical address bits 31:2
`A6`	J1 C11	every slot	the master	all	physical address bits 31:2
`A7`	J1 C12	every slot	the master	all	physical address bits 31:2
`A8`	J1 C13	every slot	the master	all	physical address bits 31:2
`A9`	J1 C14	every slot	the master	all	physical address bits 31:2
`A10`	J1 C15	every slot	the master	all	physical address bits 31:2
`A11`	J1 C16	every slot	the master	all	physical address bits 31:2
`A12`	J1 C17	every slot	the master	all	physical address bits 31:2
`A13`	J1 C18	every slot	the master	all	physical address bits 31:2
`A14`	J1 C19	every slot	the master	all	physical address bits 31:2
`A15`	J1 C20	every slot	the master	all	physical address bits 31:2
`A16`	J1 C21	every slot	the master	all	physical address bits 31:2
`A17`	J1 C22	every slot	the master	all	physical address bits 31:2
`A18`	J1 C23	every slot	the master	all	physical address bits 31:2
`A19`	J1 C24	every slot	the master	all	physical address bits 31:2
`A20`	J1 C25	every slot	the master	all	physical address bits 31:2
`A21`	J1 C26	every slot	the master	all	physical address bits 31:2
`A22`	J1 C27	every slot	the master	all	physical address bits 31:2
`A23`	J1 C28	every slot	the master	all	physical address bits 31:2
`A24`	J1 C29	every slot	the master	all	physical address bits 31:2
`A25`	J1 C30	every slot	the master	all	physical address bits 31:2
`A26`	J1 B4	every slot	the master	all	physical address bits 31:2
`A27`	J1 B6	every slot	the master	all	physical address bits 31:2
`A28`	J1 B8	every slot	the master	all	physical address bits 31:2
`A29`	J1 B10	every slot	the master	all	physical address bits 31:2
`A30`	J1 B12	every slot	the master	all	physical address bits 31:2
`A31`	J1 B14	every slot	the master	all	physical address bits 31:2
`BE0`	J1 B16	every slot	the master	all	byte enables (lanes 0-3; lane n = D[8n+7:8n])
`BE1`	J1 B18	every slot	the master	all	byte enables (lanes 0-3; lane n = D[8n+7:8n])
`BE2`	J1 B20	every slot	the master	all	byte enables (lanes 0-3; lane n = D[8n+7:8n])
`BE3`	J1 B22	every slot	the master	all	byte enables (lanes 0-3; lane n = D[8n+7:8n])
`-MRD`	J1 B24	every slot	the master	all	read cycle: the addressed card drives D
`-MWR`	J1 B26	every slot	the master	all	write cycle: the addressed card takes D (enabled lanes)
`-ACK`	J1 B28	every slot	the addressed card	the master	open-drain: a card decodes A, in the cycle's first clock; none -> BUSERROR
`-WAIT`	J1 B30	every slot	the addressed card	the master	open-drain: stretch this cycle by one clock while low (a wait state)
`CLK`	J2 A3	every slot	CPU	all	the system clock (the microcycle) and its inverse
`-CLK`	J2 A4	every slot	CPU	all	the system clock (the microcycle) and its inverse
`-RES`	J2 A5	every slot	CPU	all	reset
`PWROK`	J2 A6	every slot	backplane	CPU	power good (the backplane's +5 V supervisor, D78); low = reset, falling = power failing
`-LOCK`	J2 A7	every slot	the master	arbiter	open-drain: keep the bus for the next cycle too (an atomic read-modify-write)
`-IRQ0`	J2 A8	every slot	devices (and the debug card in DRIVE, D101)	CPU	open-drain interrupt request levels (IRQ0 = timer, the highest priority: the lowest-numbered is taken first)
`-IRQ1`	J2 A9	every slot	devices (and the debug card in DRIVE, D101)	CPU	open-drain interrupt request levels (IRQ0 = timer, the highest priority: the lowest-numbered is taken first)
`-IRQ2`	J2 A10	every slot	devices (and the debug card in DRIVE, D101)	CPU	open-drain interrupt request levels (IRQ0 = timer, the highest priority: the lowest-numbered is taken first)
`-IRQ3`	J2 A11	every slot	devices (and the debug card in DRIVE, D101)	CPU	open-drain interrupt request levels (IRQ0 = timer, the highest priority: the lowest-numbered is taken first)
`-IRQ4`	J2 A12	every slot	devices (and the debug card in DRIVE, D101)	CPU	open-drain interrupt request levels (IRQ0 = timer, the highest priority: the lowest-numbered is taken first)
`-IRQ5`	J2 A13	every slot	devices (and the debug card in DRIVE, D101)	CPU	open-drain interrupt request levels (IRQ0 = timer, the highest priority: the lowest-numbered is taken first)
`-IRQ6`	J2 A14	every slot	devices (and the debug card in DRIVE, D101)	CPU	open-drain interrupt request levels (IRQ0 = timer, the highest priority: the lowest-numbered is taken first)
`-IRQ7`	J2 A15	every slot	devices (and the debug card in DRIVE, D101)	CPU	open-drain interrupt request levels (IRQ0 = timer, the highest priority: the lowest-numbered is taken first)
`-IACK`	J2 A18	every slot	the master (the MMU / data card for the CPU)	devices	interrupt acknowledge cycle (D57): instead of -MRD, with A4:A2 = the level; the card driving that level answers -ACK and puts its vector on D7:0
`XCLK`	J2 A20	every slot	the debug card (slot 0)	CPU	an external oscillator for the CPU card (D76): the debug card's 12 MHz, or one edge per host STEP; the CPU card takes it while -XCLKEN is low
`-XCLKEN`	J2 A21	every slot	the debug card (slot 0)	CPU	low: the CPU card's oscillator is XCLK (D76); with no debug card the CPU card's pull-up holds it high
`-FAST`	J2 A19	every slot	the CPU card's clock jumper (fitted = low); the debug card alone (D101)	CPU, I/O	low: the 4 MHz clock (D74), the I/O card's timer dividing by 4; open (the backplane's pull-up): 3 MHz. Set with the power off
`-BREQ`	J2 A16	slots 0, 3–10 (radial)	the card	arbiter	this slot asks for the bus (radial)
`-BGNT`	J2 A17	slots 0, 3–10 (radial)	arbiter	the card	this slot is master from the next clock (radial)
`-BREQ3`	J2 C3	slots 2 and 0 (radial)	slot n's card	arbiter	slot n's -BREQ
`-BREQ4`	J2 C4	slots 2 and 0 (radial)	slot n's card	arbiter	slot n's -BREQ
`-BREQ5`	J2 C5	slots 2 and 0 (radial)	slot n's card	arbiter	slot n's -BREQ
`-BREQ6`	J2 C6	slots 2 and 0 (radial)	slot n's card	arbiter	slot n's -BREQ
`-BREQ7`	J2 C7	slots 2 and 0 (radial)	slot n's card	arbiter	slot n's -BREQ
`-BREQ8`	J2 C8	slots 2 and 0 (radial)	slot n's card	arbiter	slot n's -BREQ
`-BREQ9`	J2 C9	slots 2 and 0 (radial)	slot n's card	arbiter	slot n's -BREQ
`-BREQ10`	J2 C10	slots 2 and 0 (radial)	slot n's card	arbiter	slot n's -BREQ
`-BGNT3`	J2 C11	slots 2 and 0 (radial)	arbiter (the debug card alone, D101)	slot n's card	slot n's -BGNT
`-BGNT4`	J2 C12	slots 2 and 0 (radial)	arbiter (the debug card alone, D101)	slot n's card	slot n's -BGNT
`-BGNT5`	J2 C13	slots 2 and 0 (radial)	arbiter (the debug card alone, D101)	slot n's card	slot n's -BGNT
`-BGNT6`	J2 C14	slots 2 and 0 (radial)	arbiter (the debug card alone, D101)	slot n's card	slot n's -BGNT
`-BGNT7`	J2 C15	slots 2 and 0 (radial)	arbiter (the debug card alone, D101)	slot n's card	slot n's -BGNT
`-BGNT8`	J2 C16	slots 2 and 0 (radial)	arbiter (the debug card alone, D101)	slot n's card	slot n's -BGNT
`-BGNT9`	J2 C17	slots 2 and 0 (radial)	arbiter (the debug card alone, D101)	slot n's card	slot n's -BGNT
`-BGNT10`	J2 C18	slots 2 and 0 (radial)	arbiter (the debug card alone, D101)	slot n's card	slot n's -BGNT
`-BREQ0`	J2 C19	slots 2 and 0 (radial)	the debug card (slot 0)	arbiter	slot 0's -BREQ: the highest priority (D64)
`-BGNT0`	J2 C20	slots 2 and 0 (radial)	arbiter	the debug card (slot 0)	slot 0's -BGNT
`LR0`	J3 A3	slots 0–2 only	CPU or MMU/data (RSRC)	CPU, MMU/data	the CPU's result bus R, extended to the MMU / data card: addresses to MAR, store data out, load data (steered), BADADDR and the MMU's control registers in
`LR1`	J3 A4	slots 0–2 only	CPU or MMU/data (RSRC)	CPU, MMU/data	the CPU's result bus R, extended to the MMU / data card: addresses to MAR, store data out, load data (steered), BADADDR and the MMU's control registers in
`LR2`	J3 A5	slots 0–2 only	CPU or MMU/data (RSRC)	CPU, MMU/data	the CPU's result bus R, extended to the MMU / data card: addresses to MAR, store data out, load data (steered), BADADDR and the MMU's control registers in
`LR3`	J3 A6	slots 0–2 only	CPU or MMU/data (RSRC)	CPU, MMU/data	the CPU's result bus R, extended to the MMU / data card: addresses to MAR, store data out, load data (steered), BADADDR and the MMU's control registers in
`LR4`	J3 A7	slots 0–2 only	CPU or MMU/data (RSRC)	CPU, MMU/data	the CPU's result bus R, extended to the MMU / data card: addresses to MAR, store data out, load data (steered), BADADDR and the MMU's control registers in
`LR5`	J3 A8	slots 0–2 only	CPU or MMU/data (RSRC)	CPU, MMU/data	the CPU's result bus R, extended to the MMU / data card: addresses to MAR, store data out, load data (steered), BADADDR and the MMU's control registers in
`LR6`	J3 A9	slots 0–2 only	CPU or MMU/data (RSRC)	CPU, MMU/data	the CPU's result bus R, extended to the MMU / data card: addresses to MAR, store data out, load data (steered), BADADDR and the MMU's control registers in
`LR7`	J3 A10	slots 0–2 only	CPU or MMU/data (RSRC)	CPU, MMU/data	the CPU's result bus R, extended to the MMU / data card: addresses to MAR, store data out, load data (steered), BADADDR and the MMU's control registers in
`LR8`	J3 A11	slots 0–2 only	CPU or MMU/data (RSRC)	CPU, MMU/data	the CPU's result bus R, extended to the MMU / data card: addresses to MAR, store data out, load data (steered), BADADDR and the MMU's control registers in
`LR9`	J3 A12	slots 0–2 only	CPU or MMU/data (RSRC)	CPU, MMU/data	the CPU's result bus R, extended to the MMU / data card: addresses to MAR, store data out, load data (steered), BADADDR and the MMU's control registers in
`LR10`	J3 A13	slots 0–2 only	CPU or MMU/data (RSRC)	CPU, MMU/data	the CPU's result bus R, extended to the MMU / data card: addresses to MAR, store data out, load data (steered), BADADDR and the MMU's control registers in
`LR11`	J3 A14	slots 0–2 only	CPU or MMU/data (RSRC)	CPU, MMU/data	the CPU's result bus R, extended to the MMU / data card: addresses to MAR, store data out, load data (steered), BADADDR and the MMU's control registers in
`LR12`	J3 A15	slots 0–2 only	CPU or MMU/data (RSRC)	CPU, MMU/data	the CPU's result bus R, extended to the MMU / data card: addresses to MAR, store data out, load data (steered), BADADDR and the MMU's control registers in
`LR13`	J3 A16	slots 0–2 only	CPU or MMU/data (RSRC)	CPU, MMU/data	the CPU's result bus R, extended to the MMU / data card: addresses to MAR, store data out, load data (steered), BADADDR and the MMU's control registers in
`LR14`	J3 A17	slots 0–2 only	CPU or MMU/data (RSRC)	CPU, MMU/data	the CPU's result bus R, extended to the MMU / data card: addresses to MAR, store data out, load data (steered), BADADDR and the MMU's control registers in
`LR15`	J3 A18	slots 0–2 only	CPU or MMU/data (RSRC)	CPU, MMU/data	the CPU's result bus R, extended to the MMU / data card: addresses to MAR, store data out, load data (steered), BADADDR and the MMU's control registers in
`LR16`	J3 A19	slots 0–2 only	CPU or MMU/data (RSRC)	CPU, MMU/data	the CPU's result bus R, extended to the MMU / data card: addresses to MAR, store data out, load data (steered), BADADDR and the MMU's control registers in
`LR17`	J3 A20	slots 0–2 only	CPU or MMU/data (RSRC)	CPU, MMU/data	the CPU's result bus R, extended to the MMU / data card: addresses to MAR, store data out, load data (steered), BADADDR and the MMU's control registers in
`LR18`	J3 A21	slots 0–2 only	CPU or MMU/data (RSRC)	CPU, MMU/data	the CPU's result bus R, extended to the MMU / data card: addresses to MAR, store data out, load data (steered), BADADDR and the MMU's control registers in
`LR19`	J3 A22	slots 0–2 only	CPU or MMU/data (RSRC)	CPU, MMU/data	the CPU's result bus R, extended to the MMU / data card: addresses to MAR, store data out, load data (steered), BADADDR and the MMU's control registers in
`LR20`	J3 A23	slots 0–2 only	CPU or MMU/data (RSRC)	CPU, MMU/data	the CPU's result bus R, extended to the MMU / data card: addresses to MAR, store data out, load data (steered), BADADDR and the MMU's control registers in
`LR21`	J3 A24	slots 0–2 only	CPU or MMU/data (RSRC)	CPU, MMU/data	the CPU's result bus R, extended to the MMU / data card: addresses to MAR, store data out, load data (steered), BADADDR and the MMU's control registers in
`LR22`	J3 A25	slots 0–2 only	CPU or MMU/data (RSRC)	CPU, MMU/data	the CPU's result bus R, extended to the MMU / data card: addresses to MAR, store data out, load data (steered), BADADDR and the MMU's control registers in
`LR23`	J3 A26	slots 0–2 only	CPU or MMU/data (RSRC)	CPU, MMU/data	the CPU's result bus R, extended to the MMU / data card: addresses to MAR, store data out, load data (steered), BADADDR and the MMU's control registers in
`LR24`	J3 A27	slots 0–2 only	CPU or MMU/data (RSRC)	CPU, MMU/data	the CPU's result bus R, extended to the MMU / data card: addresses to MAR, store data out, load data (steered), BADADDR and the MMU's control registers in
`LR25`	J3 A28	slots 0–2 only	CPU or MMU/data (RSRC)	CPU, MMU/data	the CPU's result bus R, extended to the MMU / data card: addresses to MAR, store data out, load data (steered), BADADDR and the MMU's control registers in
`LR26`	J3 A29	slots 0–2 only	CPU or MMU/data (RSRC)	CPU, MMU/data	the CPU's result bus R, extended to the MMU / data card: addresses to MAR, store data out, load data (steered), BADADDR and the MMU's control registers in
`LR27`	J3 A30	slots 0–2 only	CPU or MMU/data (RSRC)	CPU, MMU/data	the CPU's result bus R, extended to the MMU / data card: addresses to MAR, store data out, load data (steered), BADADDR and the MMU's control registers in
`LR28`	J3 C3	slots 0–2 only	CPU or MMU/data (RSRC)	CPU, MMU/data	the CPU's result bus R, extended to the MMU / data card: addresses to MAR, store data out, load data (steered), BADADDR and the MMU's control registers in
`LR29`	J3 C4	slots 0–2 only	CPU or MMU/data (RSRC)	CPU, MMU/data	the CPU's result bus R, extended to the MMU / data card: addresses to MAR, store data out, load data (steered), BADADDR and the MMU's control registers in
`LR30`	J3 C5	slots 0–2 only	CPU or MMU/data (RSRC)	CPU, MMU/data	the CPU's result bus R, extended to the MMU / data card: addresses to MAR, store data out, load data (steered), BADADDR and the MMU's control registers in
`LR31`	J3 C6	slots 0–2 only	CPU or MMU/data (RSRC)	CPU, MMU/data	the CPU's result bus R, extended to the MMU / data card: addresses to MAR, store data out, load data (steered), BADADDR and the MMU's control registers in
`RSRC0`	J3 C7	slots 0–2 only	CPU	MMU/data	R's source, encoded (microword RSRC)
`RSRC1`	J3 C8	slots 0–2 only	CPU	MMU/data	R's source, encoded (microword RSRC)
`RSRC2`	J3 C9	slots 0–2 only	CPU	MMU/data	R's source, encoded (microword RSRC)
`RSRC3`	J3 C10	slots 0–2 only	CPU	MMU/data	R's source, encoded (microword RSRC)
`RDST0`	J3 C11	slots 0–2 only	CPU	MMU/data	R's destination, encoded (microword RDST)
`RDST1`	J3 C12	slots 0–2 only	CPU	MMU/data	R's destination, encoded (microword RDST)
`RDST2`	J3 C13	slots 0–2 only	CPU	MMU/data	R's destination, encoded (microword RDST)
`MEM0`	J3 C14	slots 0–2 only	CPU	MMU/data	memory cycle type (microword MEM)
`MEM1`	J3 C15	slots 0–2 only	CPU	MMU/data	memory cycle type (microword MEM)
`MEM2`	J3 C16	slots 0–2 only	CPU	MMU/data	memory cycle type (microword MEM)
`SIZE0`	J3 C17	slots 0–2 only	CPU	MMU/data	access size and sign-extension (from IR)
`SIZE1`	J3 C18	slots 0–2 only	CPU	MMU/data	access size and sign-extension (from IR)
`SIGNED`	J3 C19	slots 0–2 only	CPU	MMU/data	access size and sign-extension (from IR)
`SUPER`	J3 C23	slots 0–2 only	CPU	MMU/data	STATUS.S: 1 = supervisor (untranslated)
`TLBW`	J3 C24	slots 0–2 only	CPU	MMU/data	write TLBHI/TLBLO into the TLB
`CRSEL0`	J3 C20	slots 0–2 only	CPU	MMU/data	hardware control register for RSRC / RDST = CRHW
`CRSEL1`	J3 C21	slots 0–2 only	CPU	MMU/data	hardware control register for RSRC / RDST = CRHW
`CRSEL2`	J3 C22	slots 0–2 only	CPU	MMU/data	hardware control register for RSRC / RDST = CRHW
`FAULT`	J3 B4	slots 0–2 only	MMU/data	CPU	this memory cycle faulted: abort it, enter trap
`FC0`	J3 B6	slots 0–2 only	MMU/data	CPU	fault cause
`FC1`	J3 B8	slots 0–2 only	MMU/data	CPU	fault cause
`FC2`	J3 B10	slots 0–2 only	MMU/data	CPU	fault cause
`FC3`	J3 B12	slots 0–2 only	MMU/data	CPU	fault cause
`-WSTB`	J3 B14	slots 0–2 only	CPU	MMU/data	write strobe: gates every SRAM write
`STALL`	J3 B16	slots 0–2 only	MMU/data	CPU	hold the microcycle: the bus is not yet ours (arbitration) or the cycle is waiting (-WAIT)
`LOCKREQ`	J3 B18	slots 0–2 only	CPU	MMU/data	this access and the next are one atomic pair (-LOCK)
`PCINC`	J3 B22	slots 0–2 only	CPU	MMU/data	the PC's +4 and MAR <- PC: the MMU / data card keeps a shadow PC (it loads from R with the PC and counts with it), so the next fetch's address needs no R cycle
`MARPC`	J3 B24	slots 0–2 only	CPU	MMU/data	the PC's +4 and MAR <- PC: the MMU / data card keeps a shadow PC (it loads from R with the PC and counts with it), so the next fetch's address needs no R cycle
`MARINC`	J3 B26	slots 0–2 only	CPU	MMU/data	MAR += 4 (MAR is a counter): LI32's value word, then the next fetch (D59)
`CCLK`	J3 B20	slots 0–2 only	CPU	MMU/data	the CPU's clock: CLK's cycles in which the CPU commits (none while STALL, halted or between steps)
`-CPUIN`	J3 B28	slots 0–2 only	the CPU card: the pin tied to its ground	the debug card (slot 0)	low: a CPU card is in slot 1 (D102). While it is low the debug card drives nothing alone: no CLK, no -RES, none of its groups
`-MMUIN`	J3 B30	slots 0–2 only	the MMU / data card: the pin tied to its ground	the debug card (slot 0)	low: an MMU / data card is in slot 2 (D102). While it is low the debug card alone leaves that card's lines to it: D, the bus cycle's lines and the grants