Timing¶
Generated by generators/p32timing.py (D71) from every card's netlist and
generators/p32delays.py's datasheet figures — edit the generators, not this file.
A static timing analysis of the cards, alone and together over the
backplane. The gate-level simulations (D61–D67) check that the cards are
wired to do the right thing; this checks that they do it in time. Method
and assumptions: §4. Worst case is every chip at its datasheet
maximum over temperature (4.5 V, 50 pF, -40..+85 °C); typical at its
25 °C typical (p32delays.typical). A path fails if its data can arrive
after the clock edge that takes it, less that register's setup time.
1. Results¶
| Analysis | Corner | Endpoints | Failing at the design clock | Fastest clock every path allows |
|---|---|---|---|---|
| the machine at 3 MHz | worst case | 2659 | 0 | oscillator 40.4 ns: a 3.09 MHz bus clock (design: 3 MHz) |
| the machine at 3 MHz | typical | 2659 | 0 | oscillator 25.4 ns: a 4.93 MHz bus clock (design: 3 MHz) |
| the machine at 4 MHz (the clock jumper) | typical | 2659 | 0 | oscillator 25.4 ns: a 4.93 MHz bus clock (design: 4 MHz) |
| the disk card's DMA cycles (3 MHz) | worst case | 1229 | 0 | 247.0 ns (design 333.3 ns) |
| the disk card's DMA cycles (3 MHz) | typical | 1229 | 0 | 144.4 ns (design 333.3 ns) |
| the debug card alone (12 MHz timing mode) | worst case | 536 | 0 | 41.0 ns (design 41.7 ns) |
| the debug card alone (12 MHz timing mode) | typical | 536 | 0 | 26.5 ns (design 41.7 ns) |
Read data on the bus. A slave's read data must be on the backplane's D lines this long before the cycle's last edge (the path from D through the MMU / data card's load steering to the register that takes it):
- the machine at 3 MHz, worst case: 140 ns (into mmu/U76 D0)
- the machine at 3 MHz, typical: 71 ns (into mmu/U76 D0)
- the machine at 4 MHz (the clock jumper), typical: 71 ns (into mmu/U76 D0)
A device that answers from a clock of its own is held to READ_SETUP,
140 ns (p32timing_config.py): the video card's chip, whose word is on D at
least that long before the cycle ends at every phase of its clock
(generators/sim_video_timing.py). This pass fails if the machine needs more.
2. What fails¶
Each group is the endpoints of one kind of chip on one card that fail in one kind of bus cycle, with the edges' distance; its worst path in full (each step: the delay, the chip, its pins, the net reached).
3. What is not timed, and why¶
Case analysis. The machine is timed three times: a read (the
slaves drive D, the MMU / data card takes it in through its load steering,
which alone drives R), a write (the MMU / data card drives D from R,
which only the store data drives; the slaves take D in) and an
internal cycle (nothing on D; R from any source but those two). Each
card's chips on D point one way in each; signals made only from -MWR
(or only from -MRD / -IACK) do not move in the other cycles, and a
register clocked by such a strobe takes nothing then. Paths never cross
a bus twice (out of D onto R and back, say). A device's DMA drivers
(the disk card's, D75) drive the backplane only in its own cycles as
master: off in the CPU's, and timed in a run of their own with the slave
cards answering (the CPU and the MMU / data card held).
Phases. The CPU card's GAL CLKGEN makes every bus and CPU clock from the 24 MHz oscillator, so the analysis knows each one's edges in the eight-phase microcycle, and for every GAL on the oscillator which inputs it listens to at which edges.
The video card (revision 2, the HD63484 card: D103, D106, D107) is in
the machine's runs for its bus side: the decode, -ACK and -WAIT, the
cycle's GAL, the CS flip-flop on -CLK, its own registers onto D, the
command latch. Its chip and its ATmega328P have clocks of their own, so
nothing is timed into or out of them here: what the chip asks of the card
is checked with delays at every phase of its clock, and the memory side
and the dots by YACC1-D's own check of that circuit at eight corners, both
in generators/sim_video_timing.py (docs/video-card-acrtc.md §4.8).
the machine at 3 MHz:
- cpu/U3 changes only at edge 0 of the frame: GAL PANEL: the front panel's state changes at a commit, or with a button.
- the debug card's capture SRAMs are read back, and its trigger RAMs set up, only while stopped (not a path).
- the opcode mux takes R only after a FETCH (a read cycle) (not a path).
- the opcode mux takes R only after a FETCH (a read cycle) (not a path).
- the I/O card's byte devices: two clocks, -WAIT holding the first (D72) (1 more edge allowed).
- the I/O card's byte devices: two clocks, -WAIT holding the first (D72) (1 more edge allowed).
- a register-file write uses the write address (WPH selects it in phases 0-2) (not a path).
- the -IRQ lines are asynchronous to the CPU (IPEND samples them) (not a path).
- instructions come only from memory: no fetch from a device card (not a path).
- the ALU's result: read in a later microcycle than ALUGO's (D21) (1 more edge allowed).
the machine at 4 MHz (the clock jumper):
- cpu/U3 changes only at edge 0 of the frame: GAL PANEL: the front panel's state changes at a commit, or with a button.
- the debug card's capture SRAMs are read back, and its trigger RAMs set up, only while stopped (not a path).
- the opcode mux takes R only after a FETCH (a read cycle) (not a path).
- the opcode mux takes R only after a FETCH (a read cycle) (not a path).
- the I/O card's byte devices: two clocks, -WAIT holding the first (D72) (1 more edge allowed).
- the I/O card's byte devices: two clocks, -WAIT holding the first (D72) (1 more edge allowed).
- a register-file write uses the write address (WPH selects it in phases 0-2) (not a path).
- the -IRQ lines are asynchronous to the CPU (IPEND samples them) (not a path).
- instructions come only from memory: no fetch from a device card (not a path).
- the ALU's result: read in a later microcycle than ALUGO's (D21) (1 more edge allowed).
the disk card's DMA cycles (3 MHz):
- the I/O card's byte devices: two clocks, -WAIT holding the first (D72) (1 more edge allowed).
- the I/O card's byte devices: two clocks, -WAIT holding the first (D72) (1 more edge allowed).
the debug card alone (12 MHz timing mode):
- the timing mode samples the lines asynchronously, as a logic analyser does (not a path).
- the capture SRAMs are read back, and the trigger RAMs set up, only while stopped (not a path).
- the card listens or drives, never both (not a path).
Crossings. Paths between oscillators are not timed: the -IRQ lines
are sampled by IPEND, the debug card has its own oscillator for its
timing mode, the UARTs and the Picos their own clocks.
4. Open-drain lines: the release¶
An open-drain line is asserted by a driver pulling it low (timed above); it is released by its pull-up, a rise of 0.51 RC to HCT's 2.0 V:
| Line | Pull-up | Capacitance | Rise |
|---|---|---|---|
-ACK |
1k | 200 pF | 102 ns |
-BREQ0 |
10k | 50 pF | 255 ns |
-IRQ0 |
2.2k | 200 pF | 224 ns |
-IRQ1 |
2.2k | 200 pF | 224 ns |
-IRQ2 |
2.2k | 200 pF | 224 ns |
-IRQ3 |
2.2k | 200 pF | 224 ns |
-IRQ4 |
2.2k | 200 pF | 224 ns |
-IRQ5 |
2.2k | 200 pF | 224 ns |
-IRQ6 |
2.2k | 200 pF | 224 ns |
-IRQ7 |
2.2k | 200 pF | 224 ns |
-LOCK |
1k | 200 pF | 102 ns |
-WAIT |
680 | 200 pF | 69 ns |
-WAIT must be up within half a bus clock of its release (167 ns at
3 MHz, 100 at 5 MHz, less the gates: D68); -ACK before the next
cycle's decision; a radial -BREQ before the arbiter's next look.
5. Method and assumptions¶
- Delays:
generators/p32delays.py, each part's datasheet and the figures used (§6). An output into a backplane line carries 200 pF, not the datasheet's 50: about 0.06 ns a pF more for HCT, 0.02 for ACT, F, LVC and the GALs, and 3 ns for the line. A radial or local line: 50 pF. - Clocks: each register's clock pin is traced back to its oscillator through the most direct route (its clock input, not the decode that gates it); its insertion delay counts, so skew between cards does too.
- The ALU's FPGA clocks its result latches at most 200 ns after
ACLK(D21: a division takes 18 of its clocks), and the result is read in a later microcycle. - Not checked here: hold times (no datasheet gives minimum delays for most HCT parts), the FPGA's inside, metastability at the synchronizers.
6. The datasheets¶
| Part | Source |
|---|---|
| 27C256 | YACC1-D tests/video/v30_netsim.py: Atmel AT27C256R-70 doc 0014 (the font's 27C256 taken as that fast) |
| 74ABT377 | https://www.ti.com/lit/ds/symlink/sn74abt377a.pdf (BiCMOS, TTL-level outputs: no ACT / F 377 is made in DIP) |
| 74ACT00 | https://www.ti.com/lit/ds/symlink/sn74act00.pdf |
| 74ACT02 | YACC1-D tests/video/v30_netsim.py: TI CD74ACT02 |
| 74ACT04 | https://www.ti.com/lit/ds/symlink/sn74act04.pdf |
| 74ACT08 | https://www.ti.com/lit/ds/symlink/sn74act08.pdf |
| 74ACT10 | YACC1-D tests/video/v30_netsim.py: TI SN74ACT10 |
| 74ACT11 | YACC1-D tests/video/v30_netsim.py: TI SN74ACT11 |
| 74ACT157 | https://www.ti.com/lit/ds/symlink/cd74act157.pdf |
| 74ACT245 | YACC1-D tests/video/v30_netsim.py: TI SN74ACT245 |
| 74ACT273 | YACC1-D tests/video/v30_netsim.py: TI SCHS249C |
| 74ACT32 | https://www.ti.com/lit/ds/symlink/sn74act32.pdf |
| 74ACT541 | https://www.onsemi.com/download/data-sheet/pdf/74act541-d.pdf |
| 74ACT573 | YACC1-D tests/video/v30_netsim.py: TI SN74ACT573 (a transparent latch: D or LE to Q) |
| 74ACT574 | https://www.ti.com/lit/ds/symlink/sn74act574.pdf |
| 74ACT74 | https://www.ti.com/lit/ds/symlink/sn74act74.pdf |
| 74ACT86 | YACC1-D tests/video/v30_netsim.py: TI SN74ACT86 |
| 74F138 | https://www.ti.com/lit/ds/symlink/sn74f138.pdf |
| 74F151 | https://www.ti.com/lit/ds/symlink/sn74f151b.pdf |
| 74F153 | https://www.ti.com/lit/ds/symlink/sn74f153.pdf |
| 74F161 | https://www.ti.com/lit/ds/symlink/sn74f161a.pdf |
| 74F163 | https://www.ti.com/lit/ds/symlink/sn74f163a.pdf |
| 74F21 | YACC1-D tests/video/v30_netsim.py: TI SN74F21 |
| 74F253 | https://www.ti.com/lit/ds/symlink/sn74f253.pdf |
| 74F257 | https://www.ti.com/lit/ds/symlink/sn74f257.pdf |
| 74F283 | https://www.ti.com/lit/ds/symlink/sn74f283.pdf |
| 74F299 | YACC1-D tests/video/v30_netsim.py: TI SDFS071B |
| 74F521 | https://www.ti.com/lit/ds/symlink/sn74f521.pdf (the '688's pinout) |
| 74F74 | YACC1-D tests/video/v30_netsim.py: TI SDFS046A |
| 74HC05 | https://www.ti.com/lit/ds/symlink/sn74hc05.pdf (open drain: pulling down, tPHL 21; its release rises through the pull-up) |
| 74HC280 | https://www.ti.com/lit/ds/symlink/cd74hc280.pdf |
| 74HCT00 | https://www.ti.com/lit/ds/symlink/sn74hct00.pdf |
| 74HCT08 | https://www.ti.com/lit/ds/symlink/sn74hct08.pdf |
| 74HCT125 | https://www.ti.com/lit/ds/symlink/sn74hct125.pdf |
| 74HCT138 | https://www.ti.com/lit/ds/symlink/sn74hct138.pdf |
| 74HCT14 | https://www.ti.com/lit/ds/symlink/sn74hct14.pdf |
| 74HCT148 | https://www.ti.com/lit/ds/symlink/sn74hc148.pdf (no HCT datasheet found: the HC part's figures) |
| 74HCT153 | https://www.ti.com/lit/ds/symlink/cd74hct153.pdf |
| 74HCT154 | https://www.ti.com/lit/ds/symlink/cd74hct154.pdf |
| 74HCT157 | https://www.ti.com/lit/ds/symlink/sn74hct157.pdf |
| 74HCT161 | https://www.ti.com/lit/ds/symlink/cd74hct161.pdf |
| 74HCT163 | https://www.ti.com/lit/ds/symlink/cd74hct163.pdf |
| 74HCT175 | https://www.ti.com/lit/ds/symlink/cd74hct175.pdf |
| 74HCT244 | https://www.ti.com/lit/ds/symlink/sn74hct244.pdf (its -40..+125 °C column: no 85 °C one) |
| 74HCT245 | https://www.ti.com/lit/ds/symlink/sn74hct245.pdf |
| 74HCT253 | https://www.ti.com/lit/ds/symlink/cd74hct253.pdf |
| 74HCT257 | https://www.ti.com/lit/ds/symlink/sn74hct257.pdf |
| 74HCT273 | https://www.ti.com/lit/ds/symlink/sn74hct273.pdf |
| 74HCT32 | https://www.ti.com/lit/ds/symlink/sn74hct32.pdf |
| 74HCT374 | https://www.ti.com/lit/ds/symlink/sn74hct374.pdf |
| 74HCT377 | https://www.ti.com/lit/ds/symlink/cd74hct377.pdf |
| 74HCT393 | https://www.ti.com/lit/ds/symlink/cd74hct393.pdf (CP to Q3, the ripple's last bit) |
| 74HCT4002 | https://assets.nexperia.com/documents/data-sheet/74HC_HCT4002.pdf |
| 74HCT540 | https://www.ti.com/lit/ds/symlink/sn74hct540.pdf |
| 74HCT541 | https://www.ti.com/lit/ds/symlink/sn74hct541.pdf |
| 74HCT574 | https://www.ti.com/lit/ds/symlink/sn74hct574.pdf |
| 74HCT595 | https://www.ti.com/lit/ds/symlink/sn74hct595.pdf (its -40..+125 °C column) |
| 74HCT597 | https://www.ti.com/lit/ds/symlink/cd74hct597.pdf |
| 74HCT688 | https://www.ti.com/lit/ds/symlink/cd74hct688.pdf |
| 74HCT74 | https://www.ti.com/lit/ds/symlink/sn74hct74.pdf |
| 74HCT85 | https://www.ti.com/lit/ds/symlink/cd74hct85.pdf |
| 74LS145 | https://www.ti.com/lit/ds/symlink/sn74ls145.pdf (25 °C max only, 50; x1.2 for temperature) |
| 74LVC244 | https://www.ti.com/lit/ds/symlink/sn74lvc244a.pdf |
| 74LVC245 | https://www.ti.com/lit/ds/symlink/sn74lvc245a.pdf |
| 74LVC574 | https://www.ti.com/lit/ds/symlink/sn74lvc574a.pdf |
| AS6C1008 | YACC1-D tests/video/v30_netsim.py: Alliance AS6C1008-55 v1.2 |
| AS6C4008 | Alliance Memory AS6C4008 v1.4 (-55) |
| CD74HC4050 | https://www.ti.com/lit/ds/symlink/cd74hc4050.pdf |
| CY7C199 | Cypress 38-00239-E (CY7C199-15) |
| DS12C887 | ESTIMATE: its datasheet could not be fetched (Intel-mode read delay taken as 120) |
| GAL-10 | https://ww1.microchip.com/downloads/en/DeviceDoc/doc0735.pdf (ATF22V10C-10) |
| GAL-7 | https://ww1.microchip.com/downloads/en/DeviceDoc/doc0735.pdf (ATF22V10C-7; tCO 5.5 in DIP, footnote 2) |
| SST39SF010A | Microchip DS20005022C, table 11 (-55: the control store, D18) |
| SST39SF020A | Microchip DS20005022C, table 11 (-70: the boot ROM) |
| TIL311 | TI SODS001D (the latch: data 50 ns before the strobe rises and 40 ns after; the strobe low 40 ns) |
| TL16C550 | https://www.ti.com/lit/ds/symlink/tl16c550c.pdf (RD to data 45; address and CS 7 before the strobe, data 15 before WR ends) |