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P32W instruction reference

Generated by generators/gen_isaref.py from microcode/p32isa.py — do not edit. Encodings: isa-v0.md; system instructions: isa-system.md; how to use them: programmers-guide.md.

Word: OP[31:24] A[23:20] B[19:16] C[15:12] IMM16[15:0] (or OFF24[23:0]). P = privileged (traps PRIVILEGE in user mode). Branch and jump offsets count words from PC + 4.

Op Mnemonic Operands Format P Meaning
01 HALT `` N P stop the machine (emulators: exit status = r1 & 0xFF)
10 ADD rd, rs1, rs2 R rd = rs1 + rs2
11 SUB rd, rs1, rs2 R rd = rs1 − rs2
12 AND rd, rs1, rs2 R rd = rs1 & rs2
13 OR rd, rs1, rs2 R rd = rs1 | rs2
14 XOR rd, rs1, rs2 R rd = rs1 ^ rs2
15 SLL rd, rs1, rs2 R rd = rs1 << (rs2 & 31)
16 SRL rd, rs1, rs2 R rd = rs1 >> (rs2 & 31), zero fill
17 SRA rd, rs1, rs2 R rd = rs1 >> (rs2 & 31), sign fill
18 SLT rd, rs1, rs2 R rd = (rs1 < rs2) signed ? 1 : 0
19 SLTU rd, rs1, rs2 R rd = (rs1 < rs2) unsigned ? 1 : 0
1A NOR rd, rs1, rs2 R rd = ~(rs1 | rs2)
20 ADDI rd, rs1, simm16 I rd = rs1 + sext(imm)
22 ANDI rd, rs1, uimm16 IU rd = rs1 & zext(imm)
23 ORI rd, rs1, uimm16 IU rd = rs1 | zext(imm)
24 XORI rd, rs1, uimm16 IU rd = rs1 ^ zext(imm)
25 SLLI rd, rs1, shamt SH rd = rs1 << shamt
26 SRLI rd, rs1, shamt SH rd = rs1 >> shamt, zero fill
27 SRAI rd, rs1, shamt SH rd = rs1 >> shamt, sign fill
28 SLTI rd, rs1, simm16 I rd = (rs1 < sext(imm)) signed
29 SLTIU rd, rs1, simm16 I rd = (rs1 < sext(imm)) unsigned
2E LI32 rd, value32 L32 rd = the next word (two words; rd in field B)
2F LUI rd, uimm16 LUI rd = imm << 16
30 MUL rd, rs1, rs2 R rd = low 32 bits of rs1 × rs2
31 MULH rd, rs1, rs2 R rd = high 32 bits, signed × signed
32 MULHU rd, rs1, rs2 R rd = high 32 bits, unsigned × unsigned
34 DIV rd, rs1, rs2 R rd = rs1 / rs2 signed, toward zero (÷0 → −1; 0x80000000/−1 → 0x80000000)
35 DIVU rd, rs1, rs2 R rd = rs1 / rs2 unsigned (÷0 → 0xFFFFFFFF)
36 REM rd, rs1, rs2 R rd = rs1 % rs2 signed, sign of rs1 (÷0 → rs1; 0x80000000 % −1 → 0)
37 REMU rd, rs1, rs2 R rd = rs1 % rs2 unsigned (÷0 → rs1)
40 LB rd, simm16(rs1) LD rd = sext(byte at rs1 + imm)
41 LH rd, simm16(rs1) LD rd = sext(halfword), aligned
42 LW rd, simm16(rs1) LD rd = word, aligned
44 LBU rd, simm16(rs1) LD rd = zext(byte)
45 LHU rd, simm16(rs1) LD rd = zext(halfword), aligned
48 SB rs, simm16(rb) ST byte at rb + imm = rs
49 SH rs, simm16(rb) ST halfword = rs, aligned
4A SW rs, simm16(rb) ST word = rs, aligned
4C SWAP rd, simm16(rs1) LD exchange rd with the aligned word at rs1 + imm, atomically (D51)
50 BEQ ra, rb, label BR if ra == rb: PC = PC + 4 + 4 × off
51 BNE ra, rb, label BR if ra != rb
54 BLT ra, rb, label BR if ra < rb signed
55 BGE ra, rb, label BR if ra ≥ rb signed
56 BLTU ra, rb, label BR if ra < rb unsigned
57 BGEU ra, rb, label BR if ra ≥ rb unsigned
60 JMP label J PC = PC + 4 + 4 × off24
61 CALL label J push PC + 4; PC = PC + 4 + 4 × off24
62 JR rb JR PC = rb (a multiple of 4)
63 CALLR rb JR push PC + 4; PC = rb
64 RET `` N PC = pop
70 SYSCALL `` N trap SYSCALL (EPC = this instruction)
71 RTE `` N P PC = EPC; S = PS; IE = PIE
72 MFCR rd, cr / cr, rs CR P rd = control register cr
73 MTCR rd, cr / cr, rs CR P control register cr = rs
74 BREAK `` N trap BREAK
75 WAIT `` N P idle until (IPEND & IMASK) ≠ 0
76 TLBW `` N P write TLBHI / TLBLO into the TLB entry TLBHI selects
80 LBX rd, rs1, rs2[, scale] X rd = sext(byte at rs1 + rs2 × scale); scale 1, 2, 4 or 8
81 LHX rd, rs1, rs2[, scale] X rd = sext(halfword at rs1 + rs2 × scale)
82 LWX rd, rs1, rs2[, scale] X rd = word at rs1 + rs2 × scale
84 LBUX rd, rs1, rs2[, scale] X rd = zext(byte at rs1 + rs2 × scale)
85 LHUX rd, rs1, rs2[, scale] X rd = zext(halfword at rs1 + rs2 × scale)
88 SBX rd, rs1, rs2[, scale] X byte at rs1 + rs2 × scale = rd
89 SHX rd, rs1, rs2[, scale] X halfword at rs1 + rs2 × scale = rd
8A SWX rd, rs1, rs2[, scale] X word at rs1 + rs2 × scale = rd
90 LBP rd, off8(rs1), inc8 P rd = sext(byte at rs1 + off8); then rs1 += inc8
91 LHP rd, off8(rs1), inc8 P rd = sext(halfword at rs1 + off8); rs1 += inc8
92 LWP rd, off8(rs1), inc8 P rd = word at rs1 + off8; rs1 += inc8 (rs1 written last)
94 LBUP rd, off8(rs1), inc8 P rd = zext(byte at rs1 + off8); rs1 += inc8
95 LHUP rd, off8(rs1), inc8 P rd = zext(halfword at rs1 + off8); rs1 += inc8
98 SBP rd, off8(rs1), inc8 P byte at rs1 + off8 = rd; rs1 += inc8
99 SHP rd, off8(rs1), inc8 P halfword at rs1 + off8 = rd; rs1 += inc8
9A SWP rd, off8(rs1), inc8 P word at rs1 + off8 = rd; rs1 += inc8

Control registers (MFCR / MTCR)

# Name
0 STATUS
1 EPC
2 CAUSE
3 BADADDR
4 VBR
5 USP
6 IPEND
7 IMASK
8 ASID
9 TLBHI
10 TLBLO

Exception causes (CAUSE)

Code Name
1 ILLEGAL
2 PRIVILEGE
3 MISALIGNED
4 BUSERROR
5 SYSCALL
6 BREAK
8 TLBMISS_X
9 TLBMISS_R
10 TLBMISS_W
11 PROTECT
0x8000_0000 | v << 8 | n interrupt on IRQn, v = the card's vector (D57)